Cadence
Product Engineer II
About this role
Cadence builds electronic design automation software, hardware and IP used to design chips, boards and systems. This role sits on the product engineering side of Tempus, its flagship signoff ECO solution, in Bangalore. The engineer validates, improves and regresses the product to keep quality high, working with R&D, senior product engineers and release teams. Day to day it involves building product flows, defining test methods and automating processes. It suits engineers with solid timing analysis and physical design experience who are comfortable scripting.
Cadence is hiring for Product Engineer II, a full-time role based in Bengaluru.
Who can apply: MS with 2+ years or BE/BTech with 3 years. Skills: Static Timing Analysis, Verilog, TCL, Python, Perl.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Validate, improve and regress the Tempus signoff ECO product
- Work with R&D and senior product engineers to define product specifications
- Work with product release teams to improve product quality
- Develop product flows to improve quality and performance
- Define test methodologies and automate processes
What you need
- MS in Electrical/Electronics/Computer Engineering with 2+ years of experience, or BE/BTech in Electrical/Computer/Electronics Engineering with 3 years of relevant experience
- In-depth knowledge of Static Timing Analysis, signal integrity, delay calculation, timing constraints, Verilog and debugging
- Experience in timing and power closure with ECO (automated and manual)
- Familiarity with front-end/back-end design flow and physical design tools like Innovus or similar
- Scripting skills in Perl, TCL, Python or C Shell for automation
- Good communication skills for working across geographies
- Location
- Bengaluru
- Work mode
- See listing
- Experience
- MS with 2+ years or BE/BTech with 3 years
- Pay
- ₹12–22 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 27 October 2026
Skills
- Static Timing Analysis
- Verilog
- TCL
- Python
- Perl
"Est." = Hirastra's estimate based on market data, not an official figure.
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