Microchip Technology
Engineer II - CAD
About this role
Microchip's CAD group in Bangalore supports the tools and flows used in product development and works on next-generation ASIC design flow and methodology. The Engineer II role covers EDA support and building automated flows for logic synthesis, physical synthesis and sign-off timing. It involves scripting in Tcl and Python and working with business units and EDA vendors worldwide. It suits VLSI or electronics engineers with 2 to 8 years of experience.
Microchip Technology is hiring for Engineer II - CAD, a full-time role based in Bengaluru.
Who can apply: 2–8 years. Skills: Tcl, Python, Synopsys Fusion Compiler, PrimeTime, Cadence Genus.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Design, benchmark and deploy automated CAD tool flows for synthesis and sign-off timing
- Write Tcl and Python scripts to reduce flow turnaround time and track timing data
- Build and optimize front-end flows for synthesis and logic equivalence checking
- Standardize and automate validation of SDC constraints across functional and test modes
- Work with EDA vendors to test new features and troubleshoot tool failures
- Work with global business units to understand their needs
What you need
- B.E./B.Tech/M.E./M.Tech in Electronics, ECE, CS or VLSI
- 2 to 8 years of relevant experience
- Knowledge of design flows from RTL through synthesis, formal verification and timing closure
- Hands-on experience with tools such as Synopsys Fusion Compiler, DC, PrimeTime, or Cadence Genus, Tempus or Innovus
- Tcl and Python scripting
- Good verbal and written communication skills
- Location
- Bengaluru
- Work mode
- See listing
- Experience
- 2–8 years
- Pay
- ₹12–22 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 27 October 2026
Skills
- Tcl
- Python
- Synopsys Fusion Compiler
- PrimeTime
- Cadence Genus
"Est." = Hirastra's estimate based on market data, not an official figure.
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