NVIDIA
ASIC Methodology, Flow and Integration Engineer
About this role
This role sits in NVIDIA's High Speed IO team in Bengaluru and focuses on the methodology, automation and integration side of ASIC design rather than pure RTL coding. The engineer owns full-chip and block-level integration across multiple SoC and GPU projects, stitching RTL units together and managing hierarchy. Day to day it involves building Python/Perl automation, debugging connectivity and functional issues, and working with RTL, verification, physical design and architecture teams. It suits an early-career EE/ECE/CS engineer with some design integration experience who enjoys building reusable flows.
NVIDIA is hiring for ASIC Methodology, Flow and Integration Engineer, a full-time role based in Bengaluru (hybrid).
Who can apply: 1+ years. Skills: RTL integration, Python, Perl, ASIC design flows.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Own full-chip and block-level integration across NVIDIA SoC and GPU projects
- Stitch RTL units together and manage connectivity and hierarchy
- Define and improve design methodologies for scalability, quality and turnaround time
- Build Python/Perl automation pipelines for integration, debug and delivery
- Debug full-chip connectivity and functional issues across hierarchies and technology nodes
- Work with RTL, verification, physical design and architecture teams and mentor engineers on flow usage
What you need
- BS/B.Tech/MS/M.Tech in EE, ECE, CS or equivalent
- 1+ year of experience in design integration and methodologies for ASIC design
- Comprehensive understanding of IP development flows and build flows
- Good debugging, analytical and problem-solving skills
- Ability to collaborate with cross-cultural, multi-geography teams
- Exposure to AI tools like Claude and Cursor is a plus
- Location
- Bengaluru
- Work mode
- Hybrid
- Experience
- 1+ years
- Pay
- ₹20–35 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 26 October 2026
Skills
- RTL integration
- Python
- Perl
- ASIC design flows
"Est." = Hirastra's estimate based on market data, not an official figure.
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