NVIDIA
Verification Engineer, Memory Subsystem
About this role
This role is in NVIDIA's Bengaluru graphics team and focuses on verifying the GPU memory subsystem. The engineer verifies ASIC design, architecture and micro-architecture using advanced verification methodologies. The work includes understanding the design, defining verification scope, writing test plans and tests, and building verification infrastructure for complex IPs and sub-systems. It also covers performance and deadlock verification and functional coverage closure. The engineer works with architects, designers and pre- and post-silicon verification teams. It suits a B.Tech/M.Tech engineer with about two years of verification experience.
NVIDIA is hiring for Verification Engineer, Memory Subsystem, a full-time role based in Bengaluru (hybrid).
Who can apply: 2+ years. Skills: Verilog, SystemVerilog, UVM, Python, ASIC verification.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Verify ASIC design, architecture and micro-architecture using advanced verification methodologies
- Define verification scope and create test plans, tests and infrastructure for complex IPs and sub-systems
- Verify performance and deadlock behavior of the GPU memory subsystem unit
- Build reusable bus functional models, monitors, checkers and scoreboards using coverage-driven verification
- Drive functional coverage closure
- Work with architects, designers and pre- and post-silicon verification teams
What you need
- B.Tech/M.Tech with 2+ years of relevant experience
- Experience verifying complex IPs, units and sub-systems
- Experience with random stimulus, functional coverage and assertion-based verification
- Expertise in Verilog and knowledge of SystemVerilog or a similar HVL
- Familiarity with UVM/VMM and industry-standard simulation and debug tools
- Location
- Bengaluru
- Work mode
- Hybrid
- Experience
- 2+ years
- Pay
- ₹20–35 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 27 October 2026
Skills
- Verilog
- SystemVerilog
- UVM
- Python
- ASIC verification
"Est." = Hirastra's estimate based on market data, not an official figure.
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