NVIDIA
Verification Engineer - PCIE
About this role
NVIDIA's Bengaluru team is hiring a verification engineer to verify the next generation of PCI Express controllers used in its GPUs and SOCs. The engineer verifies ASIC design, architecture, golden models and micro-architecture at IP and sub-system level using methodologies such as UVM. Day to day, this involves understanding the design specification, defining verification scope, writing test plans and tests, and building verification infrastructure. The engineer works with architects, designers and pre- and post-silicon verification teams. It suits a B.Tech/M.Tech engineer with about two years of verification experience, ideally with interconnect protocols.
NVIDIA is hiring for Verification Engineer - PCIE, a full-time role based in Bengaluru (hybrid).
Who can apply: 2+ years. Skills: Verilog, SystemVerilog, UVM, PCIe, Python.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Verify PCIE controller design, architecture, golden models and micro-architecture at IP and sub-system level using UVM
- Build reusable bus functional models, monitors, checkers and scoreboards using coverage-driven verification
- Understand the design specification and define verification scope
- Develop test plans, tests and verification infrastructure
- Collaborate with architects, designers and pre- and post-silicon verification teams
What you need
- B.Tech/M.Tech with 2+ years of relevant experience
- Verification experience at unit, sub-system or SOC level using Verilog and SystemVerilog
- Background verifying IP or interconnect protocols such as PCI Express, USB or SATA
- Experience with functional coverage-based constrained random verification environments
- Experience with DV methodologies like UVM/VMM and industry-standard simulation and debug tools
- Location
- Bengaluru
- Work mode
- Hybrid
- Experience
- 2+ years
- Pay
- ₹20–35 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 27 October 2026
Skills
- Verilog
- SystemVerilog
- UVM
- PCIe
- Python
"Est." = Hirastra's estimate based on market data, not an official figure.
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