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SiFive

Engineer II, Physical Design - Cores

About this role

SiFive designs RISC-V compute platforms used in areas such as AI, automotive and data centers. This entry-level Physical Design Engineer role in Bengaluru is on the CPU cores team. The engineer works with senior colleagues to take CPU blocks from RTL to GDSII through synthesis, place and route, and timing closure. Day to day it involves analysing timing, congestion and power results and writing automation scripts. It suits graduates with strong computer architecture and digital design fundamentals who want to learn backend implementation.

SiFive is hiring for Engineer II, Physical Design - Cores, a full-time role based in Bengaluru.

Who can apply: Entry level; new graduates considered. Skills: Verilog, SystemVerilog, Python, Tcl, Physical Design.

Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.

What you'll do

  • Take CPU blocks through the physical design flow with senior engineers, including synthesis, place and route, and timing closure
  • Apply computer architecture knowledge to understand the RTL and join co-design discussions
  • Help analyse timing reports, routing congestion and power metrics to meet PPA goals
  • Write and maintain Python, Tcl or Bash scripts to automate workflows and parse reports
  • Work with RTL, microarchitecture and methodology teams

What you need

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field
  • Posting lists 3+ years of experience but is open to new graduates with excellent academic credentials
  • Solid grasp of computer architecture fundamentals such as pipelining, hazards and memory hierarchy
  • Strong digital logic knowledge and ability to read Verilog or SystemVerilog
  • Academic, project or internship exposure to VLSI design or ASIC flows
  • Proficiency in a scripting language such as Python, Tcl, Perl, C++ or Bash
  • Right to work in India and eligibility under export control laws
Location
Bengaluru
Work mode
See listing
Experience
Entry level; new graduates considered
Pay
₹12–20 LPA (Est.)
Type
Full-time job, Developer
Added
27 October 2026

Skills

  • Verilog
  • SystemVerilog
  • Python
  • Tcl
  • Physical Design

"Est." = Hirastra's estimate based on market data, not an official figure.

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