SiFive
Zebu Flow Engineer
About this role
SiFive designs RISC-V processor IP, and this role is in its System Validation team in Bengaluru. The team builds the flows used to model SiFive's RISC-V CPUs on emulators such as Synopsys ZeBu, as well as on FPGA-based platforms. The engineer maintains the build flow, debugs failures across hardware and software, and writes Python scripts to automate debugging. The role offers exposure to RISC-V processors, software and development boards. It suits an early-career engineer with logic design and Linux scripting experience.
SiFive is hiring for Zebu Flow Engineer, a full-time role based in Bengaluru.
Who can apply: 1+ years. Skills: Verilog, FPGA, Python, Bash, Linux, Synopsys ZeBu.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Build and maintain a modular flow for ZeBu models in SiFive's internal wake-based build system
- Perform root cause and failure analysis across RISC-V CPU hardware and software
- Debug using ZeBu waveform dumping, ILA and JTAG debuggers
- Develop failure hypotheses by systematically eliminating possible causes
- Create Python scripts to automate debug workflows and ZeBu runtime automation
- Work with software and validation engineering teams
What you need
- 1+ years of experience with a Bachelor's or Master's degree in Computer Science or Electronics and Communication Engineering
- Strong understanding of logic design
- Exposure to Verilog design and porting designs onto FPGA platforms
- Practical experience with Linux and scripting in Python and BASH
- Positive attitude and willingness to keep learning
- Successful background and reference checks and proof of right to work in India
- Location
- Bengaluru
- Work mode
- See listing
- Experience
- 1+ years
- Pay
- ₹10–20 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 27 October 2026
Skills
- Verilog
- FPGA
- Python
- Bash
- Linux
- Synopsys ZeBu
"Est." = Hirastra's estimate based on market data, not an official figure.
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