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Intel

Physical Design Layout Engineer

About this role

This role sits in Intel's Data Center Group in Bangalore and focuses on physical design integration of custom GPU designs covering graphics, media and SoC blocks. Day to day, the engineer verifies layouts, reviews designs at project milestones and gives feedback to the floorplan, RDL, PDN and clock teams. The goal is clean tape-in results with timely fixes and a correct-by-construction approach. It is a contract position with a hybrid work model. It suits early-career graduates with hands-on exposure to physical design through internships, projects or coursework.

Intel is hiring for Physical Design Layout Engineer, a full-time role based in Bengaluru (hybrid).

Who can apply: 0-1 years. Skills: Physical Design, Layout Verification, DRC, Floorplan, PDN, Clocking.

Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.

What you'll do

  • Perform physical design integration for GPU blocks including Gfx, Media and SOC
  • Run layout verification and reviews at key milestones
  • Give timely feedback to Floorplan, RDL, PDN and Clock teams
  • Ensure tape-in quality with timely fixes and correct-by-construction methods
  • Collaborate with other teams to meet design goals and project timelines

What you need

  • Bachelor's degree in a relevant field with 0-1 years of hands-on physical design integration experience (internships, projects, coursework or training), or a Master's degree with no prior professional experience
  • Proficiency in physical design tools and methodologies such as layout verification and design rule checks
  • Understanding of floorplan, RDL, PDN and clocking techniques
  • Preferred: strong analytical and problem-solving skills with attention to detail
  • Preferred: effective communication and collaboration skills
Location
Bengaluru
Work mode
Hybrid
Experience
0-1 years
Pay
₹8–15 LPA (Est.)
Type
Full-time job, Developer
Added
8 October 2026

Skills

  • Physical Design
  • Layout Verification
  • DRC
  • Floorplan
  • PDN
  • Clocking

"Est." = Hirastra's estimate based on market data, not an official figure.

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