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Analog Devices

Design Verification Engineer

About this role

This Design Verification Engineer role at Analog Devices in Hyderabad works on next-generation automotive connectivity SoCs based on E2B technology. These chips combine embedded processors, digital communication subsystems, firmware, security functions and mixed-signal blocks. The engineer builds SystemVerilog/UVM testbenches, integrates C models through DPI, runs regressions, analyses coverage and debugs failures before tape-out. Work is done with moderate supervision alongside design, architecture, firmware, functional safety and validation teams. It suits engineers with digital verification experience who want to specialise in automotive SoCs.

Analog Devices is hiring for Design Verification Engineer, a full-time role based in Hyderabad.

Skills: SystemVerilog, UVM, C DPI, Verilog RTL, Python, Perl.

Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.

What you'll do

  • Develop and maintain SystemVerilog/UVM verification environments, including agents, scoreboards, assertions and functional coverage
  • Write directed and constrained-random tests at block, subsystem and SoC level, and contribute to verification plans
  • Verify SoC functionality and E2B communication features, including processors, interrupts, DMA, peripherals and error handling
  • Develop C/SystemVerilog DPI interfaces and integrate C-based models
  • Run regressions, analyse coverage and failures, and debug across testbenches, RTL and embedded C
  • Support ISO 26262-related safety verification, write documentation and automate workflows with scripts

What you need

  • Proficiency in SystemVerilog and UVM
  • Experience building coverage-driven testbenches and testcases for complex digital designs
  • Experience verifying blocks, subsystems or SoCs with processors, memories, buses and interfaces
  • C programming and familiarity with C DPI integration
  • Experience with directed, constrained-random, coverage and assertion-based verification
  • Strong Verilog/SystemVerilog RTL understanding, debugging ability, and scripting in Python, Perl, TCL or shell
Location
Hyderabad
Work mode
See listing
Experience
See listing
Pay
₹10–20 LPA (Est.)
Type
Full-time job, Developer
Added
4 October 2026

Skills

  • SystemVerilog
  • UVM
  • C DPI
  • Verilog RTL
  • Python
  • Perl

"Est." = Hirastra's estimate based on market data, not an official figure.

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