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SiFive

CPU Design Verification Eng II

Location
Hyderabad
Work mode
See listing
Experience
2+ yrs exp
Pay
₹18–30 LPA (Est.)
Type
Full-time job, Developer
Added
14 November 2026

About this role

SiFive designs RISC-V processor cores used in AI, automotive, data centre, mobile and consumer chips. This Hyderabad role verifies high-performance out-of-order RISC-V CPU cores from RTL bring-up to tapeout. Day to day, the engineer writes UVM testbench components, builds random and directed tests, debugs nightly regression failures and drives coverage closure for specific core units such as the load-store unit, MMU or branch predictor. The role works directly with micro-architects and RTL designers. It suits someone with two or more years of pre-silicon verification experience and solid computer architecture fundamentals.

SiFive is hiring for CPU Design Verification Eng II, a full-time role based in Hyderabad.

Who can apply: 2+ yrs exp. Skills: SystemVerilog, UVM, SVA, Computer architecture, Python, C/Assembly.

Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.

What you'll do

  • Own verification plans for one or more out-of-order core units
  • Build and extend UVM testbench infrastructure, scoreboards, reference models and SVA assertions
  • Develop constrained-random and directed tests in C, assembly and SystemVerilog
  • Debug regression failures from logs and waveforms to root cause
  • Drive code, functional and assertion coverage closure
  • Improve regression health and verification tooling, including CI integration

What you need

  • BS or MS in Electrical/Computer Engineering, Computer Science or equivalent
  • 2+ years of pre-silicon functional verification experience (MS with strong internship/project experience considered)
  • Strong SystemVerilog and UVM skills
  • Computer architecture fundamentals: pipelining, caches, branch prediction, out-of-order execution
  • Simulator (VCS, Questa or Xcelium) and waveform debug experience
  • Bare-metal C and assembly, Python, shell/Makefile scripting and Git

Skills

  • SystemVerilog
  • UVM
  • SVA
  • Computer architecture
  • Python
  • C/Assembly

"Est." = Hirastra's estimate based on market data, not an official figure.

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