Cadence
Design Engineer II
- Location
- Bengaluru
- Work mode
- See listing
- Experience
- 2–4 yrs exp
- Pay
- ₹18–28 LPA (Est.)
- Type
- Full-time job, Developer
- Added
- 14 November 2026
- Apply by
- 31 December 2026
About this role
Cadence is an electronic design automation company that supplies software, hardware and IP used to design advanced semiconductor chips. This Design Engineer II role in Bangalore focuses on formal verification of RTL designs. Day to day, the engineer writes formal verification test plans from design specifications, builds formal environments using Verilog and SVA, and works with design teams to sign off RTL blocks. The work involves high-speed interface protocols such as AMBA, USB, PCIe, CXL, UCIe, UALink or Ethernet. It suits verification engineers with 2–4 years of experience who have already signed off blocks using formal methods.
Cadence is hiring for Design Engineer II, a full-time role based in Bengaluru.
Who can apply: 2–4 yrs exp. Skills: Verilog, SystemVerilog Assertions, Formal Verification, AMBA, PCIe, USB.
Hirastra checked that this opening is live. Apply directly through the official posting; applying is always free.
What you'll do
- Develop detailed formal verification test plans from design specifications
- Build formal verification environments using Verilog and SVA
- Collaborate with design teams to verify and sign off RTL blocks
- Apply complexity-handling and deep bug-hunting techniques to find design issues
What you need
- 2–4 years of experience
- Mandatory hands-on experience in formal verification, including sign-off of multiple RTL blocks
- Strong Verilog, SVA and formal environment development skills
- Working knowledge of a high-speed interface protocol such as AMBA, USB, PCIe, CXL, UCIe, UALink or Ethernet
- Experience with complexity handling and deep bug hunting is preferred
Skills
- Verilog
- SystemVerilog Assertions
- Formal Verification
- AMBA
- PCIe
- USB
"Est." = Hirastra's estimate based on market data, not an official figure.
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